The present invention generally relates to digital-to-analog circuits, and more particularly to a digital-to-analog converter having a circuit which compensates for a variation in the analog output dependent on a temperature change.
Recently, digital-to-analog converters (hereafter simply referred to as D/A converters) have widely been used in various fields. For example, an electron beam exposure apparatus used in LSI production processes has a D/A converter which converts a digital signal representative of the deflection position of an electron beam into an analog signal. It is required that such an electron beam exposure apparatus be precisely formed in order to realize an increasing integration density of LSIs. Thus, it is necessary to provide a highly precise D/A converter for use in the electron beam exposure apparatus. Further, the image processing fields also need a highly precise D/A converter.
FIG. 1 shows a conventional 20-bit D/A converter of a current addition type. The D/A converter shown in FIG. 1 has 20 constant-current output circuits 1.sub.20 -1.sub.1 respectively provided for 20 bits D.sub.20 -D.sub.1 of a digital signal. The bit D.sub.20 is the most significant bit (MSB), and the bit D.sub.1 is the least significant bit (LSB). For the sake of simplicity, the entire configuration of only the constant-current output circuit 1.sub.20 is illustrated in FIG. 1.
The constant-current output circuit 1.sub.20 is made up of a digital signal input terminal 2, a current switching signal generation circuit 3, n-channel MOS (Metal Oxide Semiconductor) transistors (hereafter referred to as nMOS transistors) 4-9, a constant-voltage source 10, an operational amplifier 11, a correction power source 12 and resistors 13 and 14.sub.20. The digital signal input terminal 2 is connected to an input terminal of the current switching signal generation circuit 3.
The current switching signal generation circuit 3 inputs the digital signal D.sub.20 in response to a strobe signal generated by an external circuit (not shown), outputs a signal having a phase opposite to that of the digital signal D.sub.20 to an inverting output terminal 3A, and outputs a signal in phase with the digital signal D.sub.20 to a non-inverting output terminal 3B. The inverting output terminal 3A is connected to the nMOS transistor 4, and the non-inverting output terminal 3B is connected to the gate of the nMOS transistor 5.
The nMOS transistors 4 and 5 function as a current switching circuit formed of a differential circuit. The drain of the nMOS transistor 4 is grounded, and the source thereof is connected to the source of the nMOS transistor 5 and the drain of the nMOS transistor 6. The drain of the nMOS transistor 6 is connected to an inverting input terminal of an operational amplifier 16, which has a non-inverting input terminal grounded and an output terminal connected to an analog signal output terminal 17. The output terminal of the operational amplifier 16 is also coupled to the inverting input terminal of the operational amplifier 16 through a resistor 18.
The nMOS transistors 6, 7 and 8 are connected so that they form a totem pole structure, and function to stabilize the source voltages of the nMOS transistors 4 and 5. The source of the lowermost nMOS transistor 8 is connected to the drain of the nMOS transistor 9. The gates of the nMOS transistors 6, 7 and 8 are provided with respective predetermined D.C. voltages.
The constant-voltage source 10 forms a constant-current source together with the operational amplifier 11, the nMOS transistor 9, the resistor 14.sub.20 and the constant-voltage source 19, and outputs a first constant voltage V1 necessary to form the constant current source. The constant-voltage source 10 has an output terminal connected to the non-inverting input terminal of the operational amplifier 11, which has an output terminal connected to the gate of the nMOS transistor 9. The source of the nMOS transistor 9 is connected to the inverting input terminal of the operational amplifier 11, and is coupled to an output terminal of the constant-voltage source 19 via the resistor 14.sub.20. The constant-voltage source 19 generates a second constant voltage V2 (&lt;V1) necessary to form the constant-current source, and is provided in common for the constant-current output circuits 1.sub.20 -1.sub.1.
Assuming that the resistor 14.sub.20 has a resistance R.sub.20, a current defined as (V1-V2)/R.sub.20 passes through the resistor 14.sub.20. When the digital signal D.sub.20 applied to the digital signal input terminal 2 has a high level "H", the nMOS transistor 4 is turned OFF, and the nMOS transistor 5 is turned ON, so that an output current I.sub.20 of the constant-current output circuit 1.sub.20 is such that I.sub.20 =(V1-V2)/R. On the other hand, when the digital signal D.sub.20 has a low level "L", the nMOS transistor 4 is turned ON, and the nMOS transistor 5 is turned OFF, so that the output current I.sub.20 of the constant-current output circuit 1.sub.20 is such that I.sub.20 =0.
The correction voltage source 12 generates a correction voltage .DELTA.V necessary to precisely calibrate the current passing through the resistor 14.sub.20, that is, the output current I.sub.20 of the constant-current output circuit 1.sub.20. An output terminal of the correction voltage source 12 is coupled to one end of the resistor 14.sub.20 via the resistor 13.
The constant-current output circuits 1.sub.19 -1.sub.13 are configured in the same way as the constant-current output circuit 1.sub.20 except the resistance values of the resistors 14.sub.19 -14.sub.13. The constant-current output circuits 1.sub.12 -1.sub.1 are configured in the same way as the constant-current output circuit 1.sub.20 except that the single constant-voltage source 20 generating the first voltage V1 is provided in common and the resistors 14.sub.12 -14.sub.1 (not shown for the same of simplicity) have different resistance values.
Assuming that the resistance value of the resistor 14.sub.1 is denoted by R.sub.E, the resistance values of the resistors 14.sub.20, 14.sub.19, . . . , 14.sub.1 are written as, (1/2.sup.19)R.sub.E, (1/2.sup.18),R.sub.E, . . . , R.sub.E, respectively. That is, the amounts of the currents I.sub.20, I.sub.19, . . . , I.sub.1 are calibrated so that the amounts of the currents I.sub.20, I.sub.19, . . . , I.sub.1 are equal to 2.sup.19 .times.I.sub.0, 2.sup.18 .times.I.sub.0, . . ., I.sub.0 where I.sub.0 denotes the current value of the output current I.sub.1 of the constant-current output circuit 1.sub.1. With the above-mentioned arrangement, the analog signal output by the D/A converter can has a linear characteristic.
However, it is actually difficult to require the precision of the resistors 14.sub.20 -14.sub.1 enough to realize the complete linearity. That is, there is a deviation of the resistance value from the designed value. Particularly, since the resistors 14.sub.20 -14.sub.13 of the constant-current output circuits 1.sub.20 -1.sub.13 have small resistance values, the deviations of the resistance values of these resistors greatly affect the linearity of the D/A conversion characteristic.
With the above in mind, the D/A converter shown in FIG. 1 is independently equipped with the constant-voltage sources (only sources 10 and 21 are illustrated in FIG. 1) generating the first constant voltages V1 and the correction voltage sources (only sources 12 and 22 are illustrated) generating correction voltages .DELTA.V. First, the first constant voltages V1 with respect to the constant-current circuits 1.sub.20 -1.sub.13 are adjusted so that the currents I.sub.20, I.sub.19, . . . , I.sub.13 are equal to 2.sup.19 .times.I.sub.0, 2.sup.18 .times.I.sub.0, . . . , 2.sup.12 .times.I.sub.0, respectively. Second, if there is still an error in the linearity, the correction voltages .DELTA.V are slightly adjusted so that the complete linearity can be obtained.
However, the experiments and study by the inventors show a possibility that even if the currents I.sub.20 -I.sub.13 are calibrated by the above-mentioned procedures, the linearity is destroyed due to a temperature change. In order to obtain a required precision for 20 bits, it is necessary to ensure a precision of 10.sup.-6 .OMEGA./.degree.C. or less. Even if a resistor having a small temperature coefficient equal to, for example, 10.sup.-6 .OMEGA./.degree.C. in order to obtain the above-mentioned precision, the tolerable temperature change is only 1.degree. C. Such a tolerable temperature change does not establish the stable linearity.